Single cycle linear address calculation for relative branch addressing

ABSTRACT

A method and circuit for linear space target address generation for a relative branch is described. A selection signal is generated to be used in generating a linear space target address. The generation of the linear space target address includes generating multiple corrected target addresses and selecting the linear space target address from the multiple corrected target addresses using the selection signal. The process of generating multiple corrected target addresses includes generating first, second, and third corrected target addresses. The first corrected target address is generated using an address and a displacement. The second corrected target address is generated using the address, displacement, and a second adder correction value. The third corrected target address is generated using the address, displacement, and a third adder correction value. A multiplexer outputs the first, second, or third corrected target address using the selection signal. The selection signal is generated in selection logic using a segment wrap indication and a displacement sign, where the segment wrap indication is generated based on a displacement least significant bits, a segment base, and a least significant address.

FIELD OF THE INVENTION

The present invention pertains to the field of integrated circuits. Moreparticularly, the present invention pertains to efficient addressgeneration for a segmented linear address space.

BACKGROUND OF THE INVENTION

Integrated circuits typically have address generating circuits forgenerating the addresses of code or data to be accessed from storage.Processors are an example of an integrated circuit requiring repeatedaddress generation for the retrieval of data or code from storage. Theamount of code or data that the processor can access is limited by thesize of the linear address space. The size of the linear address spaceis a function of the width in bits of the address registers in theprocessor. For example, in a processor having 32 bit registers, theprocessor can address 2³² bytes (or locations). The linear address spaceof a processor can be divided into segments. Segments can be used tohold the code, data, and a stack for a program or to hold system datastructures. If more than one program is running on a processor, eachprogram can be assigned its own set of segments. The processor thenenforces the boundaries between these segments and ensures that oneprogram does not interfere with the execution of another program bywriting into the other program's segments. The size of a segment is alsoknown as the size of the effective address space of the processor. Manypopular processors have effective address spaces and segments that are64 kilobytes in size. However, other sizes are possible.

Processors have an instruction pointer containing an instruction addresspointing to an instruction in a segment containing code to be executedby the processor. The instruction address indicates the location of theinstruction in the linear address space. The instruction address istypically translated into a physical address that is used to retrieve aninstruction from a particular location in physical memory or otherstorage device.

While executing code in a segment, a processor typically increments thecontents of the instruction pointer so that the instruction pointerpoints to the next instruction to be retrieved. However, when theprocessor encounters a relative branch instruction the contents of theinstruction pointer after execution of the relative branch instructionwill depend upon the displacement specified in the branch instruction.When the relative branch instruction is executed, a target address isgenerated using the displacement. The target address is the address ofthe next instruction to be retrieved by the processor. Upon completionof the execution of the relative branch instruction, the target addressis placed into the instruction pointer. For the case where the processoris restricted to the address space of the segment, the target addresscannot point to a location outside the code segment. Consequently, afterexecution of the relative branch instruction the instruction pointermust point to a location between the segment base and the segment baseplus the size of the effective address space. For an effective addressspace of 64 kilobytes, the instruction pointer must point to a locationbetween the segment base (lower boundary) and the segment base plusFFFFH (upper boundary).

Typically, to determine the target address in the linear address space(linear space target address) a processor will first determine theeffective space target address. To determine the effective space targetaddress, the segment base is subtracted from the instruction address toproduce the effective instruction address. The displacement is added tothe effective instruction address to produce the effective space targetaddress. Any carry that results from the sum of the displacement and theeffective instruction address is ignored. Irrespective of the value ofthe displacement, the effective space target address will be between0000H and FFFFH because the carry is ignored. After determining theeffective space target address, the processor will translate theeffective space target address to the linear address space by adding thesegment base to the effective space target address, thereby generatingthe linear space target address. Determining the target address in theeffective space and translating the effective space target address tothe linear address space is computationally intensive and typicallyrequires several clock cycles.

The performance of a processor can be significantly affected by thenumber of clock cycles required for generating target addresses forrelative branch instructions. Since address generation for relativebranch instructions is performed frequently, it would be advantageous todecrease the number of cycles.

SUMMARY OF THE INVENTION

A method and circuit for linear space target address generation for arelative branch is described. A selection signal is generated to be usedin generating a linear space target address. The generation of thelinear space target address includes generating multiple correctedtarget addresses and selecting the linear space target address from themultiple corrected target addresses using the selection signal. Theprocess of generating multiple corrected target addresses includesgenerating first, second, and third corrected target addresses. Thefirst corrected target address is generated using an address and adisplacement. The second corrected target address is generated using theaddress, displacement, and a second adder correction value. The thirdcorrected target address is generated using the address, displacement,and a third adder correction value. A multiplexer outputs the first,second, or third corrected target address using the selection signal.The selection signal is generated in selection logic using a segmentwrap indication and a displacement sign, where the segment wrapindication is generated based on a displacement least significant bits,a segment base, and a least significant address.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and notlimitation, in the figures of the accompanying drawings in which:

FIGS. 1a-1 d illustrate diagrams for linear target address calculationfor relative branches;

FIG. 2 is an electrical diagram in block form illustrating an addressgeneration unit in accordance with one embodiment of this invention;

FIG. 3 is an electrical diagram in block form illustrating analternative address generation unit in accordance with one embodiment ofthis invention;

FIG. 4 is an electrical diagram in block form illustrating analternative address generation unit in accordance with one embodiment ofthis invention;

FIG. 5 is an electrical diagram in block form illustrating analternative address generation unit in accordance with one embodiment ofthis invention;

FIG. 6 is an electrical diagram in block form illustrating analternative address generation unit in accordance with one embodiment ofthis invention; and

FIG. 7 illustrates a diagram of a computing system incorporating anaddress generation unit in accordance with one embodiment of thisinvention.

DETAILED DESCRIPTION

A method and apparatus for calculating a linear address for a targetaddress of a relative branch instruction is described below. In thefollowing description, for purposes of explanation, numerous specificdetails are set forth in order to provide a thorough understanding ofthe present invention. It would be appreciated, however, by one skilledin the art that the embodiments of the present invention may bepracticed in any integrated circuit, especially processors, withoutthese specific details. In other instances well known operations,functions and devices are not shown in order to avoid obscuring theinvention.

Several useful, preliminary descriptions will be provided below. First,the linear address space of a processor in accordance with oneembodiment of this invention is described. Second, the operation of arelative branch instruction is described. Third, a description isprovided for the problem encountered when the linear space targetaddress (linear target address) for a relative branch instruction iscalculated without first calculating the effective space target address(i.e., the target address in the effective address space or segmentspace). The description of the problem encountered in calculating thelinear target address without first calculating the effective targetaddress will provide a useful introduction to the method and apparatusof various embodiments of this invention. Finally, descriptions ofapparatus and methods in accordance with embodiments of this inventionare provided.

A processor (or other integrated circuit) in accordance with oneembodiment of this invention has a linear address space that can bedivided into segments. Each segment has a size that can be as large asthe effective address space of the processor. A segment can containcode, data, a stack or system data structures. In an embodiment inaccordance with this invention the processor has a 32 bit addressregisters allowing the processor to address 2³² locations or bytes. Thesize of a segment or the effective address space is 64 kilobytes (or 2¹⁶locations). While in an embodiment in accordance with this invention aprocessor having a 64 kilobyte effective address space and a linearaddress space of 2³² locations is described, it should be appreciatedfrom the description below that this invention can be practiced withother processors having other sizes (smaller or larger) for the linearaddress space and the effective address space.

While the processor is executing code in a segment, the processor is ina continuous process of retrieving instructions from the code segmentfor execution. The processor knows which instruction to retrieve becauseit has an instruction pointer that contains the linear space address ofthe instruction to be retrieved. After retrieving and executing aninstruction, the instruction pointer is typically incremented to pointto the next instruction to be retrieved. However, when the processorencounters a relative branch instruction the instruction pointer cannotsimply be incremented. The relative branch instruction has adisplacement as an operand. The relative branch instruction instructsthe processor to begin retrieving an instruction at some target addressthat is at some displacement from the current instruction address.Depending upon the value of the displacement, after execution of therelative branch instruction, the instruction pointer will contain atarget address which points to the next instruction to be retrieved bythe processor. Due to the segmentation of the linear address spaceirrespective of the value of the displacement, the target address cannotpoint to a location outside the code segment. A code segment has asegment base address as its lower boundary in the linear address space.The upper boundary of a code segment in the linear address space can beas large as the segment base address plus the size of the effectiveaddress space. Consequently, after execution of the relative branchinstruction the instruction pointer must point to a location between thesegment base address and the segment base address plus the size of theeffective address space. For an effective address space of 64 kilobytes,the instruction pointer must point to a location between the segmentbase (lower boundary) and the segment base plus FFFFH (upper boundary).

Having described the linear address space and the operation of arelative branch instruction of a processor in accordance with oneembodiment of this invention, the problem with calculating a lineartarget address without first calculating the effective target addresswill now be described.

Avoiding the initial step of calculating the effective target addressmeans that the linear target address needs to be calculated directly bysimply adding the instruction address and the displacement. However, thesum of the instruction address and the displacement may not yield aproper result in many instances. For example, due to segmentation, forsome values of the displacement and instruction address, the sum mayyield a linear target address which is outside the segment.

Even though the linear target address is outside the segment, the lineartarget address calculated by simply adding the instruction address andthe displacement is not completely wrong. Depending on the size of theeffective address space, a certain number of the least significant bitsof the linear target address (least significant target address) arecorrect. The number of bits that will be correct should be equivalent tothe number of bits needed to define the effective address space. Theremaining bits of the linear target address (most significant targetaddress) may be incorrect. The remaining bits or most significant targetaddress can be, however, adjusted or corrected if they are incorrect.The most significant target address that has been corrected is named acorrected most significant target address. The combination of the leastsignificant target address and the corrected most significant targetaddress will point to a target address within the segment.

To fully profit from this insight, it is necessary to determine when themost significant target address is incorrect and by how much the mostsignificant target address needs to be corrected. By knowing when themost significant target address is incorrect and by how much the mostsignificant target address needs to be corrected it will be possible todevelop several ways of generating a linear target address that lieswithin a segment.

FIGS. 1a-1 d illustrate diagrams for linear target address calculationfor relative branch instructions. FIGS. 1a-1 d will be used toillustrate situations where the most significant target address isincorrect and a correction needs to be applied. The linear address spaceshown in each of the FIGS. 1a-1 d extends from 00000000H to FFFFFFFFH.Segments illustrated in FIGS. 1a-1 d can be as large as 64 k locationsor bytes and only require four hexadecimal digits to represent aspecific location. Thus, the effective address space of a segment canextend from 0000H to FFFFH.

In FIG. 1a the segment base address (or segment lower boundary) is00000000H. Consequently, the most significant segment base (MSSB) is0000H, and the least significant segment base (LSSB) is 0000H. Theinstruction pointer in this example points to the linear address0000FF00H of a relative branch instruction having a displacement of0200H. Consequently, the most significant instruction pointer (MSIP) is0000H, and the least significant instruction pointer (LSIP) is FF00H.The displacement is sign extended so that the displacement isrepresented by a most significant displacement (MSD), which is 0000H,and a least significant displacement (LSD), which is 0200H. Since themost significant bit of the most significant hexadecimal digit of LSD is0 (or alternatively MSD is not equal to FFFFH) the sign of thedisplacement (Dsign), in this example, is positive. Dsign would benegative when the most significant bit of the most significanthexadecimal digit of LSD is 1. Where Dsign is negative, MSD would beFFFFH due to the sign extension of the displacement.

The values given above will be used to generate the linear targetaddress without first generating an effective target address. Directlygenerating a linear target address is not as simple as adding LSD andLSIP to generate a least significant linear target address and addingMSD and MSIP to generate a most significant linear target address. Foran effective address space defined by 2¹⁶ locations (or 64 kilobytes),simply adding LSD and LSIP, each of which is defined by 16 bits, willgenerate the correct least significant linear target address. However,for some values of displacement, instruction pointer, and segment base,the most significant linear target address that results from adding MSDand MSIP is invalid.

By determining the conditions for which the sum of MSD and MSIP needs tobe supplemented by a correction and determining the amount of correctionthat needs to be applied to the sum, it becomes possible to use the sumof MSD and MSIP and the conditions to arrive at a correct mostsignificant target address. It is possible to arrive at a correct mostsignificant target address because: 1) there are a finite number ofsituations for which the sum of MSD and MSIP is invalid; 2) thesituations for which the sum is invalid (or valid) can be identified;and 3) for each of the situations there is a proper correction that canbe added to the sum of MSD and MSIP.

FIG. 1a illustrates the situation for which the sum of MSD and MSIP isvalid. The sum of MSD and MSIP is the most significant target address orMSTA. FIGS. 1b-1 d illustrate the situation for which MSTA is invalid.Returning to FIG. 1a, TA is the linear target address that should resultfor the initial conditions of a segment base of 00000000H, aninstruction pointer of 0000FF00H, a displacement of 0200H, and a 16-biteffective address space. For the conditions illustrated in FIG. 1a, theMSTA is equivalent to the upper four hexadecimal digits of TA.Consequently, MSTA is valid, and no correction (CR=0) needs to be addedto MSTA to arrive at a valid or corrected most significant targetaddress (CMSTA). In other words, the difference between MSTA and themost significant 16 bits of TA is the correction, CR, that needs to beapplied to MSTA to produce the corrected most significant target address(CMSTA).

It is desirable to be able to identify the situations for which MSTAneeds to be supplemented (or not supplemented) with a correction, CR.For the situation illustrated in FIG. 1a, CR is equal to zero.Consequently, CMSTA is equivalent to MSTA. The situation illustrated inFIG. 1a can be identified using three indicators that can be derivedfrom the displacement, segment base and instruction address. Theseindicators can be used to identify the situation for which CR is goingto be 0.

The first indicator is a Carry that results from the sum of LSIP andLSD. The second indicator is a segment wrap indication that results from17-bit addition (17 bitSUM) of LSIP, LSD, and -(LSSB). If during the17-bit addition there is a carry into or out of the seventeenth bit,then the displacement from the instruction address required a wraparound a segment boundary. The third indicator is the displacement sign(Dsign) that indicates the direction of the displacement. Additionally,if a wrap occurred, by examining Dsign it can be determined whether thewrap was over the segment upper boundary or the segment lower boundary.For the situation illustrated in FIG. 1a, Carry is 1, Wrap is 1, andDsign is 0. It can be easily verified that for all other situationswhere Carry is 1, Wrap is 1, and Dsign is 0, CR will be 0. Consequently,whenever the Carry is 1, Wrap is 1 and Dsign is 0, CR will be 0, andCMSTA will simply be the sum of MSD and MSIP (MSTA) (i.e., no correctionwill be necessary).

FIG. 1b illustrates another diagram for linear target addresscalculation for a relative branch instruction. The situation illustratedin FIG. 1b has CR equal to 2. For the situation illustrated in FIG. 1b,Carry is 1, Wrap is 1 and Dsign is 1. It can be easily verified that forall other situations where Carry is 1, Wrap is 1, and Dsign is 1, CRwill be 2H. Consequently, whenever the Carry is 1, Wrap is 1 and Dsignis 1, a CR of 2H needs to be added to MSTA to generate CMSTA.

FIG. 1c illustrates another diagram for linear target addresscalculation for a relative branch instruction. The situation illustratedin FIG. 1c has CR equal to 1. For the situation illustrated in FIG. 1c,Carry is 1, Wrap is 0, and Dsign is 0. It can be easily verified thatfor all other situations where Carry is 1, Wrap is 0, and Dsign is 0, CRwill be 1 H. Consequently, whenever the Carry is 1, Wrap is 0, and Dsignis 0, a CR of 1H needs to be added to MSTA to generate CMSTA.

FIG. 1d illustrates another diagram for linear target addresscalculation for a relative branch instruction. The situation illustratedin FIG. 1d has CR equal to −1. For the situation illustrated in FIG. 1d,Carry is 0, Wrap is 1, and Dsign is 0. It can be easily verified thatfor all other situations where Carry is 0, Wrap is 1, and Dsign is 0, CRwill be −1H. Consequently, whenever the Carry is 0, Wrap is 1 and Dsignis 0, a CR of −1H needs to be added to MSTA to generate CMSTA.

The relationship between CR and the indicators is represented in Table Abelow. A value of 1 (0) for Dsign indicates that the displacement isnegative (positive). A value of 1 (0) for Carry indicates that a carryoccurred (did not occur) in adding LSIP and LSD. A value of 1 (0) forWarp indicates that a wrap occurred (did not occur) around a segmentboundary.

TABLE A Wrap Carry Displacement Sign (Dsign) Correction (CR) 0 0 0 0000H0 0 1 0000H 0 1 0 0001H 0 1 1 0001H 1 0 0 −0001H  1 0 1 0001H 1 1 00000H 1 1 1 0002H

FIGS. 1a-1 d involve situations having a 16-bit effective address space.If the relative branch instruction is not confined to an effectiveaddress space, the sum of LSD and LSIP will always add up to a validleast significant target address (LSTA). However, if there is a carryout of the sum, then MSTA has to be adjusted by a CR equal to 1H. Ifthere is no carry out of the sum, then CMSTA is equivalent to MSTA.These two additional situations can be represented in Table A by addinganother indication, 16 Bit_Branch. If 16 Bit_Branch is set to 1, thenthe relative branch instruction is confined to an effective addressspace defined by 2¹⁶ locations (or 64 kilobytes). If 16 Bit_Branch isequal to 0, then the relative branch instruction is not confined to a 64kilobyte effective address space. Table B, below, has a representationof the relationship between the four indicators and the correction CR.An ‘X’ in Table B indicates that that value of the indicator isirrelevant or a ‘don't care.’ A ‘1’ (0) in the 16 Bit_Branch columnindicates that the target address is (not) restricted to the 16-biteffective address space. A ‘0’ (1) in the Wrap column indicates that awrap around a segment boundary has not (has) occurred. A ‘0’ (1) in theCarry column indicates that a carry has not (has) occurred. A ‘0’ (1) inthe displacement sign column indicates that the displacement is apositive (negative) number.

TABLE B Displacement 16Bit_Branch Wrap Carry Sign (Dsign) Correction(CR) 0 X 0 X 0000H 0 X 1 X 0001H 1 0 0 0 0000H 1 0 0 1 0000H 1 0 1 00001H 1 0 1 1 0001H 1 1 0 0 −0001H  1 1 0 1 0001H 1 1 1 0 0000H 1 1 1 10002H

By examining Table B it should be appreciated that there are a limitednumber of corrections that need to be applied to the sum of MSIP andMSD. Specifically, the four possible corrections are as follows: 0000H;0001H; -0001H; and 0002H. By examining Table B it should also beappreciated that the indications which will trigger application of aparticular correction can be identified. Consequently, an array of16-bit adders can be used to generate in parallel several corrected mostsignificant target addresses. Each adder will add MSIP, MSD and adifferent one of the unique corrections. Depending on the indications,the output of one of the adders can be selected as the valid mostsignificant target address.

It should be appreciated that the selection can also be performed on thebasis of other indications not described herein. Alternatively, a single16-bit adder can be used to generate a valid most significant targetaddress. The 16-bit adder will add MSIP, MSD and one of the possiblecorrections. The particular correction that will be applied to the adderwill be selected from the possible corrections using the indications.

Additionally, 32-bit adders can be used instead of 16-bit adders. Where32-bit (or larger) adders are used, the number of corrections may differfrom what is described herein.

FIG. 2 illustrates a block diagram of an address generation unit 200 inaccordance with one embodiment of this invention. Generation unit 200generates a linear space target address for a relative branch withoutfirst calculating the target address in terms of the effective addressspace.

Address generation unit 200 comprises selection unit 210 and addressgeneration logic 220. Selection unit 210 receives a segment base,displacement, and an instruction address (or address), and generates aselection signal for application to address generation unit 220. Thevalue of the selection signal is a function of the segment base,displacement, displacement sign, and address. Address generation logic220 receives the displacement, the address, and the selection signal andoutputs a linear space target address. The linear space target addressis generated using the selection signal.

FIG. 3 illustrates a block diagram of an address generation unit 300 inaccordance with one embodiment of this invention. Address generationunit 300 includes selection unit 210 and address generation unit 220described in FIG. 2. Generation unit 300 generates a linear address fora target address of a relative branch without first calculating theeffective space target address.

Address generation unit 300 comprises adder (least significant adder)310, adder (segment wrap indication generator) 320 and selection logic330. While adder 310 is shown as part of selection unit 210, inalternative embodiments adder 310 may be part of address generationlogic 220. Adder 310 receives the least significant address of arelative branch instruction and the least significant displacement andgenerates a least significant target address and a carry. For the casewhere the target address is restricted to the effective address space ofa segment and the displacement needs less bits for representation thanthe bits needed to represent the linear address space, the displacementis sign extended so that the displacement is represented by a mostsignificant displacement and a least significant displacement. The totalnumber of bits in the most significant displacement and the leastsignificant displacement should equal the number of bits needed torepresent the linear address space.

Adder 320 receives a segment base, the least significant address, andthe least significant displacement and generates a segment wrapindication. Adder 320 has one more bit than the number of bits needed torepresent the effective address space. For the case where the effectiveaddress space is represented by 16 bits, adder 320 would be configuredto add 17 bits. When the seventeenth most bit in adder 320 has a carryinto it or out of it, the segment wrap indication is set to indicatethat a wrap around a segment boundary occurred. Selection logic 330receives the segment wrap indication, the carry, a 16 Bit_Branch signal,and a displacement sign. The 16 Bit_Branch signal indicates whether thetarget address is restricted to the effective address space of a segmentor can have values throughout the linear address space of the processor.The displacement sign indicates whether the displacement is a positive16 bit number or a signed 15 bit number. Selection logic 330 generates aselection signal using the segment wrap indication, the carry, the 16Bit_Branch signal, and the displacement sign.

Address generation unit 300 further comprises adder (a first adder) 340,adder (a second adder) 350, adder (a third adder) 360, multiplexer 370,and multiplexer 380. Adder 340 receives the most significantdisplacement bits and the most significant address and generates a firstcorrected most significant target address—the word “corrected” is usedas a modifier even though the correction is zero (i.e., no correction isadded to the sum of the most significant displacement bits and the mostsignificant address). Adder 350 receives the most significantdisplacement, the most significant address, and a second correction andgenerates a second corrected most significant target address. In thisembodiment the second correction has a value of 1. Multiplexer 370generates a third correction for application to adder 360. Multiplexer370 receives as inputs a 2H and a −1H. Depending on the value of thedisplacement sign, multiplexer 370 outputs the 2H or the −1H forapplication to adder 360. The output of adder 360 receives the mostsignificant displacement, the most significant address, and the thirdcorrection and generates a third corrected most significant targetaddress.

Multiplexer 380 receives the first corrected most significant targetaddress, the second corrected most significant target address, the thirdcorrected most significant target address, and the selection signal.Depending on the value of the selection signal, the multiplexer 380selects one of the three corrected most significant target addresses tooutput as the linear space most significant target address (or linearspace target address). By using address generation unit 300, the linearspace least significant target address and the linear space mostsignificant target address can be generated in a single clock cycle.

The operation of address generation unit 300 will now be described byusing the situation illustrated in FIG. 1b. For the situationillustrated in FIG. 1b, the inputs to address generation unit 300 are asfollows: the instruction least significant address (LSIP or leastsignificant address) is 8964H; the instruction most significant addressis (MSIP or most significant address) 0012H; the code segment base(segment base) is 8864H; the displacement least significant bits (LSD)are FE00H; the displacement most significant bits (MSD) are FFFFH; andthe displacement sign (Dsign) is 1. The 16 Bit_Branch has a value of 1indicating that the target address is limited to a segment defined by 16bits. For these inputs, the linear space target address should be00138764H. Thus, address generation unit 300 should generate 8764H asthe output of adder 210 and 0013H as the output of multiplexer 380.

Adder 310 adds LSD and LSIP and generates 8764H and a carry of 1 forapplication to selection logic 330. Adder 320 adds the segment base, theLSD, and the LSIP, and generates a wrap indication of 1 for applicationto selection logic 330.

Adder 340 adds MSD and MSIP, and generates an output of 0011H. Adder 350adds MSD, MSIP and a 1 (second correction), and generates an output of0012H. Whenever Dsign is 1, multiplexer 370 outputs 2 for application toadder 360. Whenever Dsign is 0, multiplexer 370 outputs −1 forapplication to adder 360. Multiplexer 370 receives Dsign, which is 1,and outputs 2 for application to adder 360. Adder 360 adds MSD, MSIP and2 (third correction), and generates an output of 0013H.

Selection logic 330 receives as inputs the following four indicators:Dsign=1; Carry=1; 16 Bit_Branch=1; and Wrap=1. For these inputs,selection logic 330 generates a selection signal for application tomultiplexer 380. The selection signal is used by multiplexer 380 toselect the output of one of adders 340-360 as the output of multiplexer380. Table C, below, has a representation of the relationship betweenthe four indicators and the adder whose output multiplexer 380 willselect using the selection signal. For the indicator values received byselection logic 330, according to Table C, selection logic 330 willproduce a selection signal that causes multiplexer 380 to select theoutput of adder 360. The values in the columns in Table C have the samemeanings as similar values have in corresponding columns in Table B.

TABLE C Displacement Output of Adder # 16Bit_Branch Wrap Carry Sign(Dsign) Selected 0 X 0 X 340 0 X 1 X 350 1 0 0 0 340 1 0 0 1 340 1 0 1 0350 1 0 1 1 350 1 1 0 0 360 1 1 0 1 350 1 1 1 0 340 1 1 1 1 360

FIG. 4 illustrates a block diagram of an address generation unit 400 inaccordance with another embodiment of this invention. Address generationunit 400 comprises adder (segment wrap indication generator) 420 andselection logic 430. Adder 420 receives a segment base, the leastsignificant address, and the least significant displacement andgenerates a segment wrap indication. Adder 420 is a 17-bit adder. Adder420 operates in a manner similar to adder 320 described in connectionwith FIG. 3. Selection logic 430 receives the segment wrap indication, a16 Bit_Branch signal, and a displacement sign. The 16 Bit_Branch signalis as described above in connection with FIG. 3. Selection logic 430generates a selection signal using the segment wrap indication, the 16Bit_Branch signal, and the displacement sign.

Address generation unit 400 further comprises adder (a first adder) 440,adder (a second adder) 450, adder (a third adder) 460, and multiplexer470. Adders 440-460 are 32-bit adders. Adder 440 receives the 32-bitdisplacement and the 32-bit instruction address (address) and generatesa first corrected target address. Adder 450 receives the 32-bitdisplacement, the 32-bit address, and a second correction and generatesa second corrected target address. In this embodiment the secondcorrection has a value of 10000H. Adder 460 receives the 32-bitdisplacement, the 32-bit address, and the third correction and generatesa third corrected target address. The third correction in thisembodiment is −10000H.

Multiplexer 470 receives the first corrected target address, the secondcorrected target address, the third corrected target address, and theselection signal. Depending on the value of the selection signal, themultiplexer 470 selects one of the three corrected target addresses tooutput as the linear space target address. The value of the selectionsignal depends on the indicators received at selection logic 430:segment wrap indication; the 16 Bit_Branch signal; and the displacementsign.

Table D, below, has a representation of the relationship between thethree indicators and the adder 430-450 whose output multiplexer 470 willselect using the selection signal. The values in the columns in Table Dhave the same meanings as similar values have in corresponding columnsin Table B.

TABLE D Output of Adder # 16Bit_Branch Wrap Displacement Sign (Dsign)Selected 0 X X 440 1 0 0 440 1 0 1 440 1 1 0 460 1 1 1 450

FIG. 5 illustrates a block diagram of an address generation unit 500 inaccordance with another embodiment of this invention. Address generationunit 500 comprises adder (least significant adder) 510, adder (segmentwrap indication generator) 520 and selection logic 530. Adder 510receives displacement least significant bits and the instruction leastsignificant address, and generates a target least significant addressand a carry. Adder 520 receives a segment base, the least significantaddress, and the least significant displacement and generates a segmentwrap indication. Adder 520 is a 17-bit adder. Adder 520 operates in amanner similar to adder 320 described in connection with FIG. 3.Selection logic 520 receives the segment wrap indication, the carry, a16 Bit_Branch signal, and a displacement sign, and generates a selectionsignal. The 16 Bit_Branch signal is as described above in connectionwith FIG. 3.

Address generation unit 500 further comprises adder 540 and multiplexer570. Adder 540 is a 16-bit adder. Multiplexer 570 receives the selectionsignal and four corrections: +2, −1, +1, and 0. Depending on theselection signal, multiplexer 570 selects one of the four correctionsfor application to adder 540. Adder 540 receives the displacement mostsignificant bits and the instruction most significant address andgenerates a linear space most significant target address.

The value of the selection signal depends on the indicators received atselection logic 520: segment wrap indication, the carry, the 16Bit_Branch signal, and the displacement sign. Table B has arepresentation of the relationship between the four indicators and thecorrection multiplexer 570 will select for application to adder 540.

FIG. 6 illustrates a block diagram of an address generation unit 600 inaccordance with another embodiment of this invention. Address generationunit 600 comprises adder (segment wrap indication generator) 620 andselection logic 630. Adder 620 receives a segment base, the leastsignificant address, and the least significant displacement andgenerates a segment wrap indication. Adder 620 is a 17-bit adder. Adder620 operates in a manner similar to adder 320 described in connectionwith FIG. 3. Selection logic 620 receives the segment wrap indication, a16 Bit_Branch signal, and a displacement sign, and generates a selectionsignal. The 16 Bit_Branch signal is as described above in connectionwith FIG. 3.

Address generation unit 600 further comprises adder 640 and multiplexer670. Adder 640 is a 32-bit adder. Multiplexer 670 receives the selectionsignal and three corrections:−10000H, +10000H, and 0H. Depending on theselection signal, multiplexer 670 selects one of the three correctionsfor application to adder 640. Adder 640 receives the 32-bitdisplacement, the 32-bit instruction address, and the correctionoutputted by multiplexer 670, and generates a linear space targetaddress.

The value of the selection signal depends on the indicators received atselection logic 620: segment wrap indication, the 16 Bit_Branch signal,and the displacement sign. Table E, below, has a representation of therelationship between the three indicators and the correction multiplexer670 will select for application to adder 640.

TABLE E 16Bit_Branch Wrap Displacement Sign (Dsign) Correction 0 X X0000H 1 0 0 0000H 1 0 1 0000H 1 1 0 −10000H  1 1 1 +10000H 

There are many variations to the embodiments described herein that arewithin the scope of this invention and that should be appreciated by oneof ordinary skill in the art. An incomplete set of variations isdescribed herein. For example, while the address generation units weredescribed herein as having a segment of 2₁₆ locations, it should beappreciated that this invention can be practiced with segments havingsmaller or larger sizes (as large as the linear address space).Furthermore, while the address generation units were described herein asbeing employed by processors having a linear address space of 2₃₂locations, it should be appreciated that this invention can be practicedwith a processor that has a linear address space that is larger orsmaller. Additionally, while the least significant adder was part of theselection unit in FIGS. 3 and 5, in alternative embodiments it can bepart of the address generation logic. Placement of an element in oneunit or another is an implementation detail that does not detract in anyway from the scope of this invention.

FIG. 7 illustrates a block diagram of computing system 700 employing anembodiment of this invention. Computing system 700 comprises processor710, read only memory (ROM) 720, random access memory (RAM) 730,input/output (I/O) subsystem 740 and data bus 750. Processor 710includes an address generation unit 715 which is similar to any of theaddress generation units described herein. Processor 710 retrievesinstructions from RAM 720 using data bus 750. Processor 710 has a linearaddress space that is divided into segments that are limited in size tothe effective address space. Consequently, when processor 710 retrievesa relative branch instruction, the target address (or address of thenext instruction to be retrieved) is limited to the boundaries of thesegment from which the relative branch instruction was obtained.Operating in a manner similar to the operation of any of the addressgeneration units described herein, the address generation unit ofprocessor 710 produces a linear address for the target address of arelative branch instruction retrieved from RAM 720. The linear addressfor the target address is used by another unit (not shown) in processor710 to generate a physical address to access a location in RAM 730. Thelocation in RAM 740 contains the next instruction to be executed byprocessor 710.

Since the speed with which a target address for a relative branchinstruction is generated has an influence on the performance of anintegrated circuit such as a processor, this invention provides a methodand apparatus for improving the performance. Generating severalcorrected addresses in parallel may improve performance. Alternatively,providing several corrections from which a valid correction can bechosen for addition to a potential target address may improveperformance.

It should be appreciated that the above methods may be performed withina processor or can be performed by a processor using a sequence ofsoftware instructions written in assembly language, C, C++, FORTRAN,BASIC, JAVA, or any other high or low-level language known in the art.For example, the above processes may be emulated on a computer systemhaving a processor that executes instructions that effectuate thefunctionality of the processes.

Thus, a method and apparatus for generating a linear address for arelative branch has been described. Although the present invention hasbeen described with reference to specific exemplary embodiments, it willbe appreciated by one of ordinary skill in the art that variousmodifications and changes may be made to these embodiments withoutdeparting from the broader spirit and scope the invention as set forthin the claims. Accordingly, the specification and drawings are to beregarded in an illustrative rather than a restrictive sense.

What is claimed is:
 1. A method comprising: generating a selectionsignal; generating a linear space target address using the selectionsignal; wherein generating a linear space target address includes:generating multiple corrected target addresses; wherein the multiplecorrected target addresses include the linear space target address; andselecting the linear space target address from the multiple correctedtarget addresses using the selection signal; and wherein generating themultiple corrected target addresses includes: generating a firstcorrected target address; generating a second corrected target address;and generating a third corrected target address.
 2. The method of claim1, wherein: generating the multiple corrected target addresses includes:generating a first corrected target address using a most significantaddress, displacement most significant bits, and a first correction;generating a second corrected target address using the most significantaddress, the displacement most significant bits, and a secondcorrection; generating a third corrected target address using the mostsignificant address and the displacement most significant bits; and thelinear space target address is a linear space most significant targetaddress.
 3. The method of claim 2, wherein generating the selectionsignal includes: generating a carry using a least significant addressand a displacement least significant bits; generating a segment wrapindication using a segment base, the displacement least significantbits, and the least significant address; and generating the selectionsignal using the carry, a displacement sign and the segment wrapindication.
 4. The method of claim 2, wherein: the linear space mostsignificant target address is the first corrected target address; andgenerating a linear space target address includes generating a linearspace least significant target address.
 5. The method of claim 1,wherein the linear space target address is the first corrected targetaddress.
 6. The method of claim 1, further comprising accessing astorage device using the linear space target address.
 7. An integratedcircuit, the circuit comprising: selection logic to output a selectionsignal; address generation logic to receive the selection signal as aninput and to supply a linear space target address using the selectionsignal; wherein the address generation logic includes, a first adder toreceive an address and a displacement, and to generate a first correctedtarget address, a second adder to receive the address, the displacement,and a second adder correction to generate a second corrected targetaddress, a third adder to receive the address, the displacement, and athird adder correction, and to generate a third corrected targetaddress, and a multiplexer to receive the first corrected targetaddress, the second corrected target address, the third corrected targetaddress, and the selection signal, and to output the linear space targetaddress; the selection logic includes, a segment wrap indicationgenerator to receive displacement least significant bits, a segmentbase, and least significant address and to generate a segment wrapindication; and the selection logic to generate the selection signalusing the segment wrap indication and a displacement sign.
 8. Thecircuit of claim 7, wherein: the address generation logic includes, afourth adder to receive a least significant address and displacementleast significant bits and to generate a carry and a linear space leastsignificant target address; the selection logic to generate theselection signal using the carry; the address is a most significantaddress; the displacement is displacement most significant bits; and thelinear space target address is a linear space most significant targetaddress.
 9. An integrated circuit, the circuit comprising: selectionlogic to output a selection signal; address generation logic to receivethe selection signal as an input and to supply a linear space targetaddress using the selection signal; wherein the address generation logicincludes, a multiplexer to receive multiple corrections and theselection signal and to output a valid correction, and an adder toreceive the valid correction, an address, and a displacement, and togenerate the linear space target address; and the selection logicincludes, a segment wrap indication generator to receive a segment base,displacement least significant bits, and a least significant address,and to generate a wrap indication; and the selection logic to generatethe selection signal using the wrap indication and a displacement sign.10. The circuit of claim 9, wherein: the address generation logicincludes, a first adder to receive a least significant address, anddisplacement least significant bits and to generate a carry and a linearspace least significant target address; the selection logic to receivethe carry and to generate the selection signal using the carry; and thelinear space target address is a linear space most significant targetaddress.
 11. A computing system, comprising: an integrated circuitincluding, selection logic to generate a selection signal; and addressgeneration logic to receive the selection signal and to generate alinear space target address using the selection signal; wherein theaddress generation logic includes, a first adder to receive an addressand a displacement, and to generate a first corrected target address, asecond adder to receive the address, the displacement, and a secondadder correction to generate a second corrected target address, a thirdadder to receive the address, the displacement, and a third addercorrection, and to generate a third corrected target address, and amultiplexer to receive the first corrected target address, the secondcorrected target address, the third corrected target address, and theselection signal, and to output the linear space target address; theselection logic includes, a segment wrap indication generator to receivedisplacement least significant bits, a segment base, and leastsignificant address and to generate a segment wrap indication; and theselection logic to generate the selection signal using the segment wrapindication and a displacement sign; and a storage device coupled to theintegrated circuit.
 12. The system of claim 11, wherein: the addressgeneration logic includes, a fourth adder to receive a least significantaddress and displacement least significant bits and to generate a carryand a linear space least significant target address; the selection logicto generate the selection signal using the carry; the address is a mostsignificant address; the displacement is displacement most significantbits; and the linear space target address is a linear space mostsignificant target address.
 13. The system of claim 12, wherein theleast significant address is a 16-bit number.
 14. The system of claim12, wherein the linear space least significant target address is a16-bit number.
 15. The system of claim 12, wherein the displacementleast significant bits are a 16-bit number.
 16. A computing system,comprising: an integrated circuit including, selection logic to generatea selection signal; and address generation logic to receive theselection signal and to generate a linear space target address using theselection signal; a storage device coupled to the integrated circuit;wherein the address generation logic includes, a multiplexer to receivemultiple corrections and the selection signal and to output a validcorrection, and an adder to receive the valid correction, an address,and a displacement, and to generate the linear space target address; andthe selection logic includes, a segment wrap indication generator toreceive a segment base, displacement least significant bits, and a leastsignificant address, and to generate a wrap indication; and theselection logic to generate the selection signal using the wrapindication and a displacement sign.
 17. A computer readable storagemedium having stored thereon instructions which when executed by aprocessor result in: generating a selection indication; generating alinear space target address using the selection indication; whereingenerating a linear space target address includes: generating multiplecorrect target addresses; wherein the multiple corrected targetaddresses include the linear space target address; and selecting thelinear space target address from the multiple corrected target addressesusing the selection indication; and wherein generating the multiplecorrected target addresses includes: generating a first corrected targetaddress; generating a second corrected target address; and generating athird corrected target address.
 18. The computer readable storage mediumof claim 17, wherein: generating the multiple corrected target addressesincludes: generating a first corrected target address using a mostsignificant address, displacement most significant bits, and a firstcorrection; generating a second corrected target address using the mostsignificant address, the displacement most significant bits, and asecond correction; generating a third corrected target address using themost significant address and the displacement most significant bits; andthe linear space target address is a linear space most significanttarget address.